1. Field of the Invention
The present invention relates to a push-pull amplifier circuit for amplifying an AC signal with controlling an idling current of its output stage.
2. Description of the Related Art
FIG. 20 shows a prior art push-pull amplifier of class AB, which is used, for example, in amplification of an audio signal and provides the amplified signal to a speaker. When the push-pull amplifier is used, for example, in mobile electronic equipment such as a portable telephone, high power efficiency and the lowest possible power consumption are demanded.
In the output stage of the circuit, an N-channel FET 10 and a P-channel FET 11 are connected in series between a conductor having a power supply potential VDD and a conductor having a power supply potential VSS. Currents IP and IN flowing through the transistors 10 and 11 are determined by gate potentials VG1 and VG2 of the transistors 10 and 11, respectively.
In the input stage of the circuit, a constant current source 12, an N-channel FET 13, a P-channel FET 14, and an N-channel FET 15 are connected in series between the conductor having the potential VDD and the conductor having the potential VSS.
The gate and drain of the N-channel FET 13 are mutually connected and the gate of the N-channel FET 13 is connected to the gate of the N-channel FET 10. The gate and drain of the P-channel FET 14 are mutually connected and the gate of the P-channel FET 14 is connected to the gate of the P-channel FET 11. A voltage between the gate and source of the N-channel FET 13 is substantially equal to the threshold voltage Vthn thereof and a voltage between the gate and source of the P-channel FET 14 is substantially equal to the threshold voltage Vthp thereof. Accordingly, a difference (VG1xe2x88x92VG2) between the gate potentials VG1 and VG2 of the transistors 10 and 11 is substantially constant independently of an input potential VI, having a signal and a bias voltage components, that is applied to the gate of the N-channel FET 15. The transistors 13 and 14 constitute gate potential difference circuit 16.
By means of the constant current source 12, a substantially constant current ID flows through the between-gate potential difference circuit 16 and the N-channel FET 15. The voltage VD between the source and drain of the constant current source 12 changes depending on the gate potential VI of the N-channel FET 15, and VG1=VDDxe2x88x92VD is determined by VD. The constant current source 12 and the N-channel FET 15 constitute an input circuit 17.
With rise in the input voltage VI from a value, the drain current ID of the constant current source 12 is going to increase, and the voltage VD between the source and drain of the constant current source 12 rises (see FIG. 21(A)). Thereby, the gate potentials VG1 and VG2 each fall, resulting in decreasing in the current IP, increasing in the current IN and falling in output voltage VO.
One end of a load 18 is connected to a node between the N-channel FET 10 and the P-channel FET 11, and the other end thereof is connected to a conductor having a power supply potential, for example, (VDD+VSS)/2. A current IL=IPxe2x88x92IN flows through the load 18. When IP greater than IN, that is IL greater than 0, an idle current flowing from VDD through the transistors 10 and 11 to VSS is equal to IN. When IP less than IN, that is IL less than 0, an idle current flowing from VDD through the transistors 10 and 11 to VSS is equal to IP. Relations of each of the current IP and IN with the input voltage VI are as shown in FIG. 21(B).
The idle current is required to have a magnitude at some extent in order to improve a linearity of the output signal with the input signal. The idle current generally tends to increase as the output current IL decreases (FIG. 21(B)). Further, since the idle current changes depending on deviations of process in device fabrication and of temperature in operating, the minimum idle current has to be ensured in design so as to be more than a predetermined value in the worst conditions conceivable. Therefore, according to conditions, wasteful idle current flows which causes increase in power consumption. Especially, an idle current in the output stage of a push-pull amplifier cannot be neglected because its magnitude is rather large.
In order to decrease the idle current, in a push-pull amplifier disclosed in JP 96-23247A, the idle current is detected in a monitoring part having current mirror circuits, its detected value is compared with a current of a constant current source and the idle current is controlled so as to be of a predetermined value in response to the compared result.
In the output stage of that push-pull amplifier, as shown in FIG. 22, an N-channel FET 10 and a P-channel FET 11 are connected between conductors having a power supply potentials VDD and VSS in series in the order reverse to the case of FIG. 20. The P-channel FET 11 and a P-channel FET 14 whose gate and drain are connected mutually constitute a current mirror circuit, and therefore a voltage between the source and gate of the P-channel FET 14 is substantially equal to the threshold voltage Vthp thereof. Likewise, the N-channel FET 10 and an N-channel FET 13 whose gate and drain are connected mutually constitute a current mirror circuit and therefore, a voltage between the source and gate of the N-channel FET 13 is substantially equal to the threshold voltage Vthn thereof. For example, in a case where the power supply voltage (VDDxe2x88x92VSS) is 3.0 V and the threshold voltages Vthp and Vthn are both 0.5 V, a potential difference between the gates of the transistors 11 and 10 are approximately 3.0xe2x88x920.5xc3x972=2.0 V regardless of an input signal.
However, when the power supply voltage (VDDxe2x88x92VSS) changes, the potential difference between the gates of the transistors 11 and 10 changes in a slave manner following the change in the power voltage (VDDxe2x88x92VSS). Therefore it becomes hard to control the idle current so as to be a predetermined value.
Further, letting xcexc=(W/L of the transistor 11)/(W/L of the transistor 14), where a gate width is W and a gate length is L, the maximum value of the current IP flowing through the transistor 11 is limited to a value of xcexc times the maximum current flowing through the transistor 14. Since a size of the transistor 11 has a limit on its size, the maximum value of the current IP is also limited to a value under the limitation on the size. This limitation applies to the current IN as well.
Referring back to the push-pull amplifier of FIG. 20, the current IP is controlled by the voltage between the gate and source of the N-channel FET 10. However, with rising in the gate potential VG1, an output voltage VO also rises. Therefore, the voltage between the gate and source is approximately equal to the threshold voltage Vthn of the N-channel FET 10, resulting in that the maximum value of the current IP is limited. This limitation also applies to the current IN.
In addition, in the push-pull amplifier of FIG. 20, the maximum amplitude of the output voltage VO is limited in the following way. That is, since a relation VO≈VDDxe2x88x92VDxe2x88x92Vthn holds, the minimum value of the source-drain voltage VD with which a constant current source 12 can function is, for example, of about 0.1 V and the threshold voltage Vthn is of about 0.5 V, therefore, the maximum value of the output voltage VO is of about (VDDxe2x88x920.6) V. In this maximum state, since a source potential of the N-channel FET 10 is much higher than the power supply voltage VSS, the threshold voltage Vthn is higher due to a substrate bias effect, which causes a further fall in the maximum value of the output voltage VO. Since the push-pull amplifier is substantially symmetrical with respect to the middle potential between the power supply potentials VDD and VSS, likewise the minimum value of the output voltage VO is of about (VSS+0.6) V, resulting in that the maximum amplitude of the output voltage VO is limited especially when VDD is low.
Next, another problem of a push-pull amplifier will be described.
FIG. 23 shows an operational amplifier circuit, which is disclosed in JP 96-8654A, comprising a differential amplifier 50 and a class AB push-pull amplifier 60X in the succeeding stage. This operational amplifier circuit is used in amplifying, for example, an audio signal provided to a speaker.
In a case where the operational amplifier is used in mobile electronic equipment such as a portable telephone, there arise demands for high power efficiency and as small power consumption as possible. Further, in a case of being used in small sized mobile electronic equipment, since a current drive capability is relatively low, increase therein is required.
In a push-pull output circuit 61 of the amplifier 60X, transistors 11 and 10 are connected in series between conductors having power supply potentials VDD and VSS. The output voltage VA of the differential amplifier 50 is provided to the gate of the transistor 11 while the voltage VB generated by a control circuit 62 in response to the voltage VA is provided to the gate of the transistor 11.
In the control circuit 62, T1 and T4 each are P-channel FETs and T2, T3 and T5 each are N-channel FETS.
The transistors T2 and T3 constitutes a current mirror circuit and the current I3 flowing through the transistor T3 is proportional to the current I1 flowing through the transistor T2. If the proportional coefficient which is determined by transistor size is 1, a relation I3=I1 holds. The transistor T4 constitutes a constant current source whose gate is applied with a constant voltage VB0 and the constant current I4 thereof is equal to a sum of the current I3 flowing through the transistor T3 and the current I5 flowing through the transistor T5. Therefore, a relation I5=I4xe2x88x92I1 holds. Further, the transistors T5 and 10 constitute a current mirror circuit, the current IN flowing through the transistor 10 is proportional to the current I5, and letting the proportional coefficient be k, a relation IN=kxc2x7I5 holds. Therefore, the following equation holds.
IN=kxc2x7(I4xe2x88x92I1)xe2x80x83xe2x80x83(1)
A load 18 and a DC power supply 19 are connected in series between an output node, which is between the transistors 11 and 10, and the conductor having the power supply potential VSS.
FIG. 24 shows the relation of the voltage VA with each of the currents IN and IP. The relation between the voltages VA and VB is determined by the control circuit 62, and the current IN is one when the voltage VB depending on the VA is applied to the gate of the transistor 10.
At a point VA=VSG in FIG. 24, the current IP flowing through the transistor 11 and the current IN flowing through the transistor 10 are equal to each other, and thereby a current flowing through the load 18, that is, output current, is zero.
As the voltage VA rises from stable biased voltage in which the output current is zero, the current IP decreases. While the current I1 decreases, and thereby the current IN increases according to the above described equation (1). Therefore, a current (INxe2x88x92IP) flows from the load 18 to the amplifier 60X.
As the voltage VA falls from that stable biased voltage, the current IP increases. While the current I1 increases, and thereby the current IN decreases according to the equation (1). Therefore, the current (IPxe2x88x92IN) flows from the amplifier 60x to the load 18.
An idle current Iidl flowing through the transistors 11 and 10 has a value Min (IP, IN) which means a smaller one of the currents IP and IN. As described above, the value becomes the maximum Im when the output current is zero.
Denoting the minimum and maximum of the current I1 as I1max and I1min, respectively, the maximum Imax and minimum Imin of the current IN are respectively expressed by the following equations derived from the above equation (1).
Imax=kxc2x7(I4xe2x88x92I1min)xe2x80x83xe2x80x83(2)
xe2x80x83Imin=kxc2x7(I4xe2x88x92I1max)xe2x80x83xe2x80x83(3)
As Imax is larger, a load drive capability is higher, while as Imin is smaller, the idle current Iidl is smaller.
However, if a value of k or I4 is increased in order to improve the load drive capability, Imin also increases, thereby increasing the idle current Iidl. Contrary to this, if a value of k or I4 is decreased in order to decrease the idle current Iidl, Imax decreases, thereby lowering the load drive capability. That is, improvement of the load drive capability and decrease in the idle current are incompatible requirements with each other.
Accordingly, it is an object of the present invention to provide a push-pull amplifier circuit that can expand an output current range.
It is another object of the present invention to provide a push-pull amplifier circuit that can expand an output voltage range.
It is a further object of the present invention to provide a push-pull amplifier circuit that can achieve both to improve load drive capability and to reduce in an idle current.
Hereinafter, the term merely xe2x80x9csignalxe2x80x9d means a voltage signal or a current signal.
In the first aspect of the present invention, as shown in FIG. 1 for example, there is provided a push-pull amplifier circuit comprising: a push-pull output circuit having first and second transistors (11 and 10) connected in series between first and second power supply potentials, a conductivity of the second transistor being opposite to that of the first transistor, each of the first and second transistors having a control input; a control input potential difference circuit (16A) having first and second ends (OP and ON) being connected to the control inputs of the first and second transistors and a control input for receiving a control signal (VG3) to adjust a voltage between the first and second ends in response to the control signal; and an input circuit (17) for changing potentials of the first and second ends in response to an input signal with keeping the voltage substantially constant. With the first aspect of the present invention, it is not necessary to connect a transistor in diode connection between the control input of the first transistor and the first or second power supply potential, that is, between the gate and source of the first transistor or between the base and emitter of the first transistor, and it is not necessary to connect a transistor in diode connection between the control input of the second transistor and the second or first power supply potential, that is, between the gate and source of the second transistor or between the base and emitter of the second transistor.
Further, because the output of the amplifier is obtained from the drains or collectors of the first and second transistors, the minimum of the absolute value of the difference between the output potential and the first power supply potential or the absolute value of the difference between the output potential and the second power supply potential can be reduced down to about 0.1 V.
Accordingly, limitations on potential range at the control inputs of the first and second transistors can be alleviated, and as a result, the output current range and the output voltage range of the push-pull amplifier circuit can be expanded.
In the second aspect of the present invention, as shown in FIG. 11 for example, there is provided a push-pull amplifier circuit comprising: a push-pull output circuit having first and second transistors (11 and 10) connected in series between first and second power supply potentials, a conductivity of the second transistor being opposite to that of the first transistor, the first transistor having a control input for receiving an input signal, the second transistor having a control input for receiving a control signal; a control circuit for, in response to the input signal VA, generating the control signal VB by multiplying the input signal VA by xcex1 and shifting the multiplied input signal xcex1xc2x7VA byxe2x88x92xcex2, wherein a is a substantially predetermined positive value and xcex2 is a substantially predetermined value having a sign same as that of ((the input signal)xe2x88x92(the control signal)).
The current I flowing through the second transistor is substantially expressed by the following equations.
I=gm(VBxe2x88x92Vth) for VB greater than Vthxe2x80x83xe2x80x83(4)
I=0 for VB less than Vthxe2x80x83xe2x80x83(5)
Herein, gm designates the transconductance of the second transistor, and Vth designates the threshold voltage of the second transistor.
The following equation holds in the above second aspect.
VB=xcex1xc2x7VAxe2x88x92xcex2xe2x80x83xe2x80x83(6)
When this equation is substituted into the equation (4), the following equation is obtained.
I=gmxc2x7(VAxe2x88x92(xcex2+Vth)/xcex1)xe2x80x83xe2x80x83(7)
In actual fact, in order to properly reduce a cross-over distortion, circuit design is performed so that the minimum of I may be a small positive value that is not zero.
By selecting a properly large value of xcex1, the current drive capability can be improved according to the equation (7). Further, by selecting a proper value of xcex2 together with this proper large value of xcex1, it is possible to set VB at VB=Vth in the equation (4), that is, at VA=(xcex2+Vth)/xcex1 in the equation (7), whereby I=0.
With the second aspect of the present invention, both improvement of the load drive capability and reduction in an idle current can be achieved.
In the third aspect of the present invention, there is provided a push-pull amplifier circuit as defined in the second aspect, as shown in FIG. 9 for example, further comprising a constant current source connected in parallel to the second output transistor, wherein the xcex1 and xcex2 have such values that a current flowing through the second transistor is substantially zero when a current flowing through the first transistor is larger than a minimum value with a load being operably connected to the push-pull output circuit.
In this case, letting the current of the constant current source be IO, equations corresponding to the above equations (4) and (5) are expressed as follows.
I=gm(VBxe2x88x92Vth)+IO for VB greater than Vthxe2x80x83xe2x80x83(8)
I=0 for VB less than Vthxe2x80x83xe2x80x83(9)
Thus, as shown in FIG. 10, when VB less than Vth, no current flows through the load and the idle current IO flowing through the first transistors can be made constant. In addition to this, the idle current 10 can be determined independently of the maximum value Imax of I. Accordingly, not only improvement of the load drive capability and decrease in the idle current simultaneously can be attained in an effective manner, but also circuit design can be easier.
Other aspects, objects, and the advantages of the present invention will become apparent from the following detailed description taken in connection with the accompanying drawings.